The present invention is directed, in general, to gate arrays and, more specifically, to a system and method for instantiating logic blocks within a field-programmable gate array (FPGA).
The rate of change of technology in the computer and telecommunications fields has generated an increased focus on the ability of designers and marketers of new applications to implement their products more quickly. This is especially true in the area of digital design. Some conventional approaches use Application Specific Integrated Circuits (ASICs), which are especially built to provide a specific implementation of a design. Alternately, designers may also use a more general type of integrated circuit called a gate array that contains unconnected logic elements such as two-input NAND gates.
These gate arrays may be programmed to produce a specific application of a digital design thereby allowing a general logic building block to be tailored for a specific application. This approach may typically reduce the time-to-market for new designs. Regular gate arrays are manufactured by designing and adhering top layers that provide the interconnecting pathways. Although this final masking stage is less costly and may be accomplished more quickly than designing an ASIC, it still requires at least one special manufacturing step.
Field Programmable Gate Arrays (FPGAs) alleviate the need for this special manufacturing step by allowing the specific application instructions to be programmed directly into the gate array. This characteristic replaces the special manufacturing step with a programming step that may be accomplished in the field or as required. This has further reduced the time-to-market for new designs. Additionally, corrections and upgrades to the design may be more easily accomplished through the use of FPGAs.
A single copy of a running program is referred to as an instance or instantiation of the program. In object-oriented programming, an instantiation is typically a member of a class of objects. For example, xe2x80x9cLassiexe2x80x9d is an instantiation of the class xe2x80x9cdogxe2x80x9d. Currently, multiple instantiations of a program often require that each of the instantiations be loaded separately into a memory device, such as an FPGA. The use of Very Large-scale Integrated Circuit Programming Language (VHDL) implementations allow multiple instantiations of a logic block to be created.
However, in order to instantiate a logic block in VHDL, a designer must currently change the VHDL source file and then re-link and re-fit the entire file before downloading it to the FPGA. This typically assumes the availability of a host processor to modify the instantiation in the FPGA and may require a high-bandwidth interface to download the resulting bitstream. This is particularly true if an application requires that the logic be time-shared between different functions, or that it be reconfigured frequently.
Accordingly, what is needed in the art is a more appropriate way that an FPGA may internally manage the instantiation of logic blocks.
To address the above-discussed deficiencies of the prior art, the present invention provides a copying logic block for, and a method of, programming an FPGA and a modular music synthesis processor incorporating the copying logic block or the method. In one embodiment, the copying logic block includes: (1) a block receiver that receives an instantiable logic block via a programming port of the FPGA and (2) a block instantiator, coupled to the block receiver, that creates multiple instantiations of the instantiable logic block within the FPGA in response to a command received via the programming port without requiring each of the multiple instantiations to enter the FPGA via the programming port. In an alternate embodiment of the present invention, the copying logic block is loadable into the FPGA via the programming port.
The present invention recognizes that it is not necessary to burden the programming port with carrying all of the instantiations of a given logic block. Rather, the instantiable logic block can be sent through the programming port and into the FPGA once, and instantiated internally by way of the copying logic block.
In one embodiment of the present invention, the block instantiator assigns physical ports to the multiple instantiations. In a related embodiment, the block instantiator tracks assignment of physical ports to the multiple instantiations. In an embodiment to be illustrated and described, the block instantiator maintains a list of unassigned and assigned physical ports.
In one embodiment of the present invention, the copying logic block further includes a block deallocator, coupled to the block instantiator, that deallocates an instantiation of the instantiable logic block in response to a further command received via the programming port. Thus, the present invention contemplates, but does not require, that one or more of the multiple instantiations may be deallocated, and perhaps replaced with other instantiations of the same or another instantiable logic block.
In one embodiment of the present invention, the logic block is embodied in Very Large-scale Integrated Circuit Hardware Description Language (VHDL). Those skilled in the pertinent art are familiar with VHDL and its current practice with respect to FPGA programming. The present invention can be carried out in any object-oriented language of other Hardware Description Languages, however.
In one embodiment of the present invention, the copying logic block persists once the multiple instantiations are created. This assumes that the copying logic block remains of use after initial instantiation. Some embodiments of the present invention benefit from continuing dynamic instantiation of logic blocks. Alternatively, the copying logic block may be deallocated after initial instantiation and its space freed for containing other logic blocks as may be advantageous.
In one embodiment of the present invention, the instantiable logic block is a structured audio processor. Such structured audio processor may be employed to process or generate one or more channels of audio data in a modular music synthesis processor. Those skilled in the pertinent art will understand, however, that the principles of the present invention are not limited to audio applications.
The foregoing has outlined, rather broadly, preferred and alternative features of the present invention so that those skilled in the art may better understand the detailed description of the invention that follows. Additional features of the invention will be described hereinafter that form the subject of the claims of the invention. Those skilled in the art should appreciate that they can readily use the disclosed conception and specific embodiment as a basis for designing or modifying other structures for carrying out the same purposes of the present invention. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention in its broadest form.